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| Siemens Power Hybrid for SMPS Preliminary Data SPH 4692 Bipolar IC Features q Fold-back characteristics provides overload protection for q q q q q q q external components Burst operation under secondary short-circuit condition implemented Protection against open or a short of the control loop Switch-off if line voltage is too low (undervoltage switch-off) Line voltage depending compensation of fold-back point Soft-start for quiet start-up without noise generated by the transformer Chip-over temperature protection implemented (thermal shutdown) On-chip ringing suppression circuit against parasitic oscillations of the transformer P-DIP-18-4 Power MOSFET q VDS = 600 V q R DS ON = 3.0 q Repetitive Avalanche Type SPH 4692 Ordering Code Q67000-A5069 Package P-DIP-18-4 The Siemens Power Hybrid SPH 4692 contains the SMPS IC TDA 4605-3 as well as the SIEMENS POWER MOSFET in a P-DIP-18 package. The IC TDA 4605-3 controls the MOS-power transistor and performs all necessary control and protection functions in free running flyback converters. Because of the fact that a wide load range is achieved, this IC is applicable for consumer as well as industrial power supplies. Semiconductor Group 1 02.95 SPH 4692 The serial circuit and primary winding of the flyback transformer are connected in series to the input voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the switch-off period the energy is fed to the load via the secondary winding. By varying the switch-on time of the power transistor, the IC controls each portion of energy transferred to the secondary side such that the output voltage remains nearly independent of load variations. The required control information is taken from the input voltage during the switch-on period of the transistor and from a regulation winding during the switch-off period. A new cycle will start if the transformer has transferred the stored energy completely into the load. In the different load ranges the switched-mode power supply (SMPS) behaves as follows: No-load Operation The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be a little bit higher or lower than the nominal value depending of the design of the transformer and the resistor of the control voltage divider. Nominal Operation The switching frequency is reduced with increasing load and decreasing AC-voltage. The output voltage is only dependent on the load. Overload Point Maximal output power is available at this point of the output characteristic. Overload The energy transferred per operation cycle is limited at the top. Therefore the output voltages declines by secondary overloading. Pin Configuration Control IC Pin 1 Pin 2 Pin 3 Pin 4 Pin 15 Pin 16 Pin 17 Pin 18 Regulating voltage Primary current simulation Primary voltage detector Ground Push-pull output Supply voltage Soft-start Zero detector Pin Configuration Power MOSFET Pin 5, 12 Pin 6-11 Pin 13 Pin 14 N.C. MOSFET-Drain MOSFET-Source MOSFET-Gate Semiconductor Group 2 SPH 4692 Pin Definitions and Functions Pin No. 1 Function Information Input Concerning Secondary Voltage. By comparing the regulating voltage - obtained from the regulating winding of the transformer - with the internal reference voltage, the output impulse width on pin 15 is adapted to the load of the secondary side (normal, overload, short-circuit, no load). Information Input Regarding the Primary Current. The primary current rise in the primary winding is simulated at pin 2 as a voltage rise by means of external RC-element. When a value is reached that's derived from the regulating voltage at pin 1, the output impulse at pin 15 is terminated. The RC-element serves to set the maximum power at the overload point set. Input for Primary Voltage Monitoring. In the normal operation V3 is moving between the thresholds V3H and V3L (V3H > V3 > V3L). V3 < V3L: SMPS is switched OFF (line voltage too low). V3 > V3H : Compensation of the overload point regulation (controlled by pin 2) starts at V3H : V3L = 1.7. Ground Not connected MOSFET-Drain Not connected MOSFET-Source MOSFET-Gate Output: Push-pull output provides 1 A for rapid charge and discharge of the gate capacitance of the power MOS-transistor. Supply Voltage Input. From it a stable internal reference voltage VREF and the switching thresholds V16A , V16E , V16 max and V16 min for the supply voltage detector is formed. If V16 > V16E then VREF is switched on and switched off when V16 < V16A . In addition the logic is only enabled for V16 min > V16 . Input for Soft-Start. Start-up will begin with short pulses by connecting a capacitor from pin 7 to ground. Input for the Oscillation Feedback. After starting oscillation, every zero transit of the feedback voltage (falling edge) triggers an output impulse at pin 15. The trigger threshold is at + 50 mV typical. 2 3 4 5 6-11 12 13 14 15 16 17 18 Semiconductor Group 3 SPH 4692 Block Diagram Semiconductor Group 4 SPH 4692 Circuit Description Application Circuit The application circuit shows a flyback converter for video recorders with an output power rating of 25 W. The circuit is designed as a wide-range power supply for AC-line voltage of 180 to 264 V. The AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by C1. The NTC limits the rush-in current. In the period before the switch-on threshold is reached the IC is supplied via resistor R1; during the start-up phase it uses the energy stored in C2, under steady state conditions the IC receives its supply voltage from transformer winding n1 via diode D1. The switching transistor T1 is a BUZ 92. The parallel connected capacitor C3 and the inductance of primary winding n2 determine the system resonance frequency. The R2-C4-D2 circuitry limits overshoot peaks, and R13 protects the gate of T1 against static charges. During the conductive phase of the power transistor T1 the current rise in the primary winding depends on the winding inductance and the mains voltage. The network consisting of R4-C5 is used to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage is fed into pin 2 of the IC. The RC-time constant given by R4-C5 must be designed that way that driving the transistor core into saturation is avoided. The ratio of the voltage divider R10/R11 is fixing a voltage level threshold. Below this threshold the switching power supply shall stop operation because of the low mains voltage. The control voltage present at pin 3 also determines the correction current for the fold-back point. This current added to the current flowing through R4 and represents an additional charge to C5 in order to reduce the turn-on phase of T1. This is done to stabilize the fold-back point even under higher main voltages. Regulation of the switched-mode power supply is via pin 1.The control voltage of winding n1 during the off period of T1 is rectified by D3, smoothed by C6 and stepped down at an adjustable ratio by R5, R6 and R7. The R8-C7 network suppresses parasitic overshoots (transformer oscillation). The peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage applied across the control winding, and hence the output voltages, are at the desired level. When the transformer has supplied its energy to the load, the control voltage passes through zero. The IC detects the zero crossing via series resistors R9 connected to pin 18. But zero crossings are also produced by transformer oscillation after T1 has turned off if outputs is short-circuited. Therefore the IC ignores zero crossings occurring within a specified period of time after T1 turn-off. The capacitor C8 connected to pin 17 causes the power supply to be started with shorter pulses to keep the operating frequency outside the audible range during start-up. On the secondary side, three output voltages are produced across winding n3 to n5 rectified by D4 to D6 and smoothed by C9 to C11. Resistor R12 is used as a bleeder resistor. Fusable resistors R15 and R16 protect the rectifiers against short-circuits in the output circuits, which are designed to supply only small loads. Semiconductor Group 5 SPH 4692 Block Diagram Pin 1 The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR in the regulating and overload amplifier. The output of this stage is fed to the stop comparator. If the control voltage is rather small at pin 1 an additional current is added by means of current source which is controlled according the level at pin 17. This additional current is virtually reducing the control voltage present at pin 1. Pin 2 A voltage proportional to the drain current of the switching transistor is generated there by the external RC-combination in conjunction with the primary current transducer. The output on this transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage V2 exceeds the output voltage of the regulations amplifier, the logic is reset by the stop comparator and consequently the output of pin 15 is switched to low potential. Further inputs for the logic stage are the output for the start impulse generator with the stable reference potential VST and the supply voltage motor. Pin 3 The down divide primary voltage applied there stabilized the overload point. In addition the logic is disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary voltage monitor block. Pin 4 Ground Pin 15 In the output stage the output signals produced by the logic are shifted to a level suitable for MOSpower transistors. Pin 16 From the supply voltage V16 are derived a stable internal references VREF and the switching threshold V16 A , V16 E , V16 max and V16 min for the supply voltage monitor. All references values (VR , V2 B , VST) are derived from VREF . If V16 > VVE , the VREF is switched on and switched off when V16 < V16 A. In addition, the logic is released only for V16 min < V16 < V16 max . Pin17 The output of the overload amplifier is connected to pin 17. A load on this output causes a reduction in maximal impulse duration. This function can be used to implement a soft start, when pin 17 is connected to ground by a capacitor. Semiconductor Group 6 SPH 4692 Pin 18 The zero detector controlling the logic block recognizes the transformer being discharged by positive to negative zero crossing of pin 18 voltage and enables the logic for a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse. Start-Up Behaviour The start-up behaviour of the application circuit per page 133 is represented on page 135 for a line voltage barely above the lower acceptable limit time t0 the following voltages built up: - V16 corresponding to the half-wave charge current over R1 - V2 to V2 max (typically 6.6 V) - V3 to the value determined by the divider R10/R11. The current drawn by the IC in this case is less than 0.8 mA. If V16 reaches the threshold V16 E (time point t1), the IC switches on the internal reference voltage. The current draw max. rises to 12 mA. The primary current-voltage reproducer regulates V2 down to V2B and the starting impulse generator generates the starting impulses from time point t5 to t6. The feedback to pin 18 starts the next impulse and so on. All impulses including the starting impulse are controlled in width by regulating voltage of pin 1. When switching on this corresponds to a shortcircuit event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width depending on the regulating voltage feedback (the IC operates in the overload range). The IC operates at the overload point. Thereafter the peak values of V2 decrease rapidly, as the starting attempt is aborted (pin 15 is switched to low). As the IC remains switched on, V16 further decreases to V16. The IC switches off; V16 can rise again (time point t4) and a new start-up attempt begins at time point t1. If the rectified alternating line voltage (primary voltage) collapses during load, V3 can fall below V3 A , as is happening at time point t3 (switch-on attempt when voltage is too low). The primary voltage monitor then clamps V3 to V3 S until the IC switches off (V16 < V16 A). Then a new start-up attempt begins at time point t1. Semiconductor Group 7 SPH 4692 Regulation, Overload and No-Load Behaviour When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is 400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V15 = H). The peak voltage value at pin 2 increases up to V2S max. If the secondary load is further increased, the overload amplifier begins to regulate the pulse width downward. This point is referred to as the overload point of the power supply. As the IC supply voltage V16 is directly proportional to the secondary voltage, it goes down in accordance with the overload regulation behaviour. If V16 falls below the value V16 min, the IC goes into burst operation. As the time constant of the half-wave charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back to the pulse width tpk. This pulse width must remain possible, in order to permit the IC to start-up without problems from the virtual short-circuit, which every switching on with V1 = 0 represents. If the secondary side is unloaded, the loading impulses (V15 = H) become shorter. The frequency increases up to the resonance frequency of the system. If the load is further reduced, the secondary voltages and V16 increase. When V16 = V16 max, the logic is blocked. The IC converts to burst operation. This renders the circuit absolutely safe under no-load conditions. Behaviour when Temperature Exceeds Limit An integrated temperature protection disables the logic when the chip temperature becomes too high. The IC automatically interrogates the temperature and starts as soon as the temperature decreases to permissible values. Semiconductor Group 8 SPH 4692 Absolute Maximum Ratings TA = - 20 to 85 C Parameter Symbol min. Control Circuit Voltage pin 1 pin 2 pin 3 pin 15 pin 16 pin 17 pin 1 pin 2 pin 3 pin 4 pin 15 pin 16 pin 17 pin 18 Limit Values typ. max. Unit Remarks V1 V2 V3 V15 V16 V17 I1 I2 I3 I4 I 15 I 16 I 17 I 18 Tj Tstg - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 3 V16 20 3 3 3 V V V V V V mA mA mA A A A mA mA C C Supply voltage Current - 1.5 - 0.5 -5 - 40 1.5 0.5 3 3 125 125 tp 50 s; v 0.1 tp 50 s; v 0.1 tp 50 s; v 0.1 Junction temperature Storage temperature Power MOSFET Drain current Pulsed drain current Gate source voltage Power dissipation Single pulse Avalanche Energy ID ID pulse VGS PD EAS - 20 2 4.5 + 20 1.7 220 A A V W mJ TA = 25 C TA = 25 C TA = 25 C ID = 3.3 A; VDD = 50 V R GS = 25 ; L = 30 mH limited by Tj limited by Tj max Repetitive avalanche Energy Avalanche current repet. or non-repet. Junction temperature EAR IAR Tj 6 3.3 150 mJ A C Semiconductor Group 9 SPH 4692 Absolute Maximum Ratings (cont'd) TA = - 20 to 85 C Parameter Storage temperature Thermal resistance system-air Symbol min. Limit Values typ. max. 125 70 C K/W Cooling surface 100 mm2 - 40 Unit Remarks Tstg R th SA Operating Range Parameter Symbol min. Control Circuit Supply voltage Ambient temperature Heat resistance Junction to environment Junction to package Limit Values typ. max. Unit Remarks V16 TA R th JE R th JG 7.5 - 20 15.5 85 100 70 V C K/W K/W IC "on" measured at pin 4 Semiconductor Group 10 SPH 4692 Characteristics TA = 25 C; VS = 10 V Parameter Symbol min. Control Circuit Start-Up Hysteresis Start-up current Switch-on voltage Switch-off voltage Switch-on current Switch-off current Limit Values typ. max. Unit Test Condition Test Circuit I 16 E0 V16 E V16 A I 16 E1 I 16 A1 11 4.5 0.6 12 5 11 10 0.8 13 5.5 mA V V mA mA V16 = V16 E 1 1 1 V16 = V16 E V16 = V16 A 1 1 Voltage Clamp (V16 = 10 V, IC switched-off) At pin 2 (V16 < V16 E) At pin 3 (V16 < V16 E) Control Range Control input voltage Voltage gain of the control circuit in the control range V2 max V3 max 5.6 5.6 6.6 6.6 8 8 V V I 2 = 1 mA I 3 = 1 mA 1 1 V1 R - VR 390 400 43 410 mV dB 2 VR = d (V2S - V2B)/ dV1 f = 1 kHz 2 Primary Current Simulation Voltage Basic value V2 B 0.97 1.00 1.03 V 2 Overload Range and Short-Circuit Operation Peak value in the range of secondary overload Peak value in the range of secondary short circuit operation V2 B V2 K 2.9 2.2 3.0 2.4 3.1 2.9 V V V1 = V1R - 10 mV V1 = 0 2 2 Fold-Back Point Correction Fold-back point correction current - I2 300 500 650 A V3 = 3.7 V 1 Semiconductor Group 11 SPH 4692 Characteristics (cont'd) TA = 25 C; VS = 10 V Parameter Symbol min. Generally Valid Data (V16 = 10 V) Voltage of the Zero Transition Detector Positive clamping Negative clamping Threshold value Suppression of transformer ringing Input current Push-Pull Output Stage Saturation voltages: Pin 15 sourcing Pin 15 sinking Pin 15 sinking Output Slew Rate Rising edge Falling edge + dV15/ dt 70 100 V/s V/s 2 2 Limit Values typ. max. Unit Test Condition Test Circuit V18 P V18 N V18 S t UL - I 18 40 3.0 0 0.75 - 0.2 50 3.4 3.8 4 V V mV s A I 18 = 1 mA I 18 = 1 mA 2 2 2 2 V18 = 0 VSat 0 VSat V VSat V 1.5 1.0 1.4 2.0 1.2 1.8 V V V I 15 = - 0.1 A I 15 = + 0.1 A I 15 = + 0.5 A 1 1 1 - dV15/dt Reduction of Control Voltage Current to reduce the control voltage -I 1 50 A V17 = 1.1 V Semiconductor Group 12 SPH 4692 Characteristics (cont'd) TA = 25 C; VS = 10 V Parameter Symbol min. Protection Circuit Undervoltage protection for V 16: voltage at pin 15 = V15 min if V16 < V16 min Undervoltage protection for V 16: voltage at pin 15 = V15 min if V16 > V16 max Undervoltage protection for Vac: voltage at pin 15 = V15 min if V3 < V3 A Limit Values typ. max. Unit Test Condition Test Circuit V16 min 7.0 7.25 7.5 V 2 V16 max 15.5 16 16.5 V 2 V3 A 985 1000 1015 mV V2 = 0 V 1 Over temperature: at the Tj given chip temperature the IC will switch V15 to 150 C 2 V15 min Voltage at pin 3 if one of V3 Sat the protection function was triggered; (V3 will be clamped until V16 < V16 A) Current drain during burst operation 0.4 0.8 V I 3 = 750 A 1 I 16 8 mA V3 = V2 = 0 V 1 Semiconductor Group 13 SPH 4692 Characteristics (cont'd) TA = 25 C; VS = 10 V Parameter Symbol min. Power MOSFET Static Ratings Drain source breakdown VBR DSS voltage Gate threshold voltage controlled by TDA 4605-3 Zero gate voltage drain current Zero gate voltage drain current Drain source on-state resistance Dynamic Ratings Forward transconductance Input capacitance 600 2.1 3.0 4.0 V V Limit Values typ. max. Unit Test Condition Test Circuit VGS = 0 V; I D = 0.25 mA VGS = VDS; I D = 1 mA Tj = 25 C VDS = 600 V VGS = 0 V Tj = 125 C VDS = 600 V VGS = 0 V VGS th I DSS 0.1 1.0 A I DSS 10 100 A R DS ON 2.6 3.0 g fs 2.1 3.0 S VDS = 2 x I D x R DS (ON) max I D = 2.0 A VGS = 0 V VDS = 25 V f = 1 MHz VGS = 0 V VDS = 25 V f = 1 MHz VGS = 0 V VDS = 25 V f = 1 MHz VCC = 300 V VGS = 10 V I D = 2.3 A R GS = 50 C Iss 600 900 pF Output capacitance C Oss 65 100 pF Reverse transfer capacitance Turn-on delay time C rs 25 40 pF t d ON 10 15 ns Semiconductor Group 14 SPH 4692 Characteristics (cont'd) TA = 25 C; VS = 10 V Parameter Rise time Symbol min. Limit Values typ. 50 max. 70 ns Unit Test Condition Test Circuit tr VCC = 30 V VGS = 10 V I D = 2.3 A R GS = 50 VCC = 30 V VGS = 10 V I D = 2.3 A R GS = 50 VCC = 30 V VGS = 10 V I D = 2.3 A R GS = 50 Turn-off delay time t d OFF 70 95 ns Fall time tf 40 55 ns Reverse Diode Continuous reverse drain current Pulsed reverse drain current Diode forward Reverse recovery time IS I SM VSD t rr 0.52 3.2 1.0 350 1.4 A A V ns VGS = 0 V I F = 2.8 A VR = 100 V I F = 2.8 A dI F/dt = 100 A/s Reverse recovery charge Q rr 2.5 C VR = 100 V I F = 2.8 A dI F/d t = 100 A/s Semiconductor Group 15 SPH 4692 Test Circuit 1 Test Circuit 2 Semiconductor Group 16 SPH 4692 Application Circuit Semiconductor Group 17 SPH 4692 Diagrams Semiconductor Group 18 SPH 4692 Semiconductor Group 19 SPH 4692 Start-Up Hysteresis Semiconductor Group 20 SPH 4692 Operation in Test Circuit 2 Semiconductor Group 21 SPH 4692 Start-Up Current as a Function of the Ambient Temperature Overload Point Correction as a Function of the Voltage at Pin 3 Semiconductor Group 22 |
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